ASIC Design Engineer San Diego, CA : Multimedia IP Core Front-End Digital design Required Skills: - ASIC IP Core development and deployment - Verilog/VHDL coding - Tool: NC-SIM/Modeltech/VCS experience, Verilog/VHDL Linting, Synopsys synthesis, Formal Verification, CDC, Power Analysis - Have owned and handled designs ~500K gates. - Excellent communication skills Required Education: BSEE with equivalent experience Preferred Education: MSEE