ASIC Design /Verification engineers
We have3 opening for ASIC Design /Verification engineers with same client and same location Job#1 - Experience with implementation of OFDM based modem designs (802.11a, g, n, ac or WiMax or LTE) - Excellent knowledge of Verilog, SystemVerilog, C++, Perl, Makefiles - Experience in developing Mixed-Signal chips for low-power hand-held products Job#2 · BSEE with 7 years or MSEE with 5 years · Strong background on micro-architecture, Verilog RTL logic design and module level verification · Familiar with synthesis, Static Timing analysis tools · Capable to construct simple test bench for module level verification · Familiar with 802.11 Wireless LAN standard and protocol · WIFI MAC development experience · Hands on laboratory bring-up and debug experience · Comfortable with C/C++, Perl scripts, Makefiles · Experience in power analysis tools (Synopsys or Cadence) a plus · Experience/knowledge in SystemVerilog a plus Job#3 . Self Motivated, Team Player that can work with various groups . Ability to multi-task various verification activities . BS in Electrical Engineering required, prefer MS Electrical Engineering or Computer Science . 4+ years in ASIC verification. Experience in building Verification environments using SystemVerilog, VMM/OVM/UVM . Past experience in Low-power verification is a huge plus . Experience building verification environment using Constraint Random, SystemVerilog Assertions . Strong knowledge of ARM processor and it’s integration, AXI, APB, DMA, DDR controllers . Familiar with peripheral devices like I2C, SDIO, USB, SDRAM, USIM, MIPI interface . Prior experience in verifying OFDM[A]/DMT based systems, digital modems, GSM/GPS/CDMA, Ethernet Physical Layer or other communication systems would be helpful . Knowledge of Shell scripting, Perl, and Makefiles
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