Our client is a global leading computer components manufacturer seeking an Engineer capable to providing logic verification of RTL descriptions for chipsets. This individual will be performing ASIC verification based on architectural/micro-architectural specification review and analysis followed with definition of verification requirements. RESPONSIBILITIES: Develop tests and test bench components from high level verification plans Debug failing tests Define functional coverage space Implement coverage monitors Analyze test coverage space Regress running and debugging failing tests Design and develop test bench collateral QUALIFICATIONS: 5-10 years experience in ASIC logic verification Strong software skills with experience using 1 or more of the following languages: System Verilog/Verilog, Perl, C/C++ Experience with RTL simulators, VCS preferred Experience specifying and developing test bench components, specifying, developing, and debugging functional tests, and experience specifying, implementing and analysing functional coverage Strong debug abilities Good interpersonal skills and the ability to work in a highly cooperative team environment across many time zones Strong background specifying and developing random test environments preferred Excellent problem solving and interpersonal skills Additional Skills (Nice to Have): OVM/UVM Full chip integration experience Chipset and/or SoC experience Estimated Length of Assignment: 18 Months Number of Available Positions: 4 Estimated Hours per Week: 40 hours % of travel required: none Telecommuting: up to 5%