FULL TIME Position 1 - Senior design engineer - Position 2 - Staff level asic verification engineer Responsibilities: * Responsible for micro-architecture of complex modules in ASICs * Responsible for RTL Coding, Block level simulations and Synthesis * Work closely with backend team during P&R and timing closure * Work closely with Silicon Validation and System Integration teams to Bringup the ASIC and the system Requirements: * Candidate's must have a Bachelor's Degree or higher in EE with very good academics. Master’s degree preferred. * 5+ years of experience in ASIC Design. * Participation in at least 1 full ASIC cycle as a designer from Arch to Bringup * Good knowledge and experience in RTL/Synthesis based ASIC design methodology and tools * Good in logic design skills (micro-architecture development and implementation). * Networking and packet based protocol experience is desired * Experience in packet or hybrid systems is preferred * Must have good communication skills. * Must have ability and desire to work as a team Interested candiates submit your resume to prerita@ptsol.com or call Prerita @ 408-962-4865