Asic Design and Verification Engineer
Asic Design and Verification Engineer Santa Clara, CA Hello, Please take a look at the below requirement details and let me know if you are comfortable with it along with your updated resume. Role: Asic Design and Verification Engineer Location: Santa Clara, CA Duration: 12 months + Kindly find below job description highlighted and which our client is looking for. Primary skill required Special skill required Number of open positions Number of years of Exp. Location ASIC Verification Engineer . Verification environments using SystemVerilog, VMM/OVM/UVM . OFDM based modem designs, . Mixed-Signal based low-power design techniques, . C++/Perl/Makefiles 3 4 to 7 years Santa Clara, CA ASIC Verification Engineer . Self Motivated, Team Player that can work with various groups . Ability to multi-task various verification activities . BS in Electrical Engineering required, prefer MS Electrical Engineering or Computer Science . 4+ years in ASIC verification. Experience in building Verification environments using SystemVerilog, VMM/OVM/UVM . Past experience in Low-power verification is a huge plus . Experience building verification environment using Constraint Random, SystemVerilog Assertions . Strong knowledge of ARM processor and it’s integration, AXI, APB, DMA, DDR controllers . Familiar with peripheral devices like I2C, SDIO, USB, SDRAM, USIM, MIPI interface . Prior experience in verifying OFDM[A]/DMT based systems, digital modems, GSM/GPS/CDMA, Ethernet Physical Layer or other communication systems would be helpful . Knowledge of Shell scripting, Perl, and Makefiles 3 to 7 4 to 7 years Hope to hear soon from you. Regards, Feroz mohd
Santa Clara, CA
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