Title: Analog Design Engineer Duration: 6 to 18 months Location: Hillsboro, OR No. of roles: 2 Telecommuting: No Years of Experience amp; Expertise Level: BS EE; 5-9 years Project Description: --------------------------- Group needs to augment ASIC execution in the team. CW will assist the DE Leads in executing structural design including Synthesis runs, Pamp;R, APR, Performance Verification involving static timing analysis, FEV and layout verification. Daily Responsibilities: ------------------------------ Work with the IP development team on above tasks. Publish a task plan and execute to that plan. Necessary Skills (Must Have): ---------------------------------------- Verilog RTL skills, Synthesis and Timing analysis experience, Synopsys ICC, DFT tools, scripting in PERL and Shell. Additional Skills Desired (Nice to Have): ------------------------------------------------------ Unix. Communication and team skills. NOTE: Only US Citizens or GC Holders being considered for this role.