Senior Design IP Application Engineer San Jose, CA As a Senior Application Engineer at the Client, you will consult with customers on Industry leading Design IP products. The role will require you to participate in customer evaluations to demonstrate the applicability and integration of Cadence’s industry leading Design IP portfolio. The candidate must have a strong background in design flow from Architecture, Micro architecture, implementation, Synthesis and timing. Design experience in PCIEe, Ethernet, Memory, High speed I/O is desirable BSEE or equivalent required with 7+ years of relevant experience Strong Verilog Skills Strong interest and understanding of design methodologies Knowledge of, experience with or project background in Verilog simulation (using Incisive, VCS, Questa, or similar), Synopsys DesignCompiler, Synopsys PrimeTime, perl, TCL and UNIX shell scripting Ability to understand system-level implications (hardware, firmware, software, and interaction with CPUs and other modules) of IP decisions Strong problem solving skills